The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Patent No.:

US 7940501 B1

PDF
Full Text
Expired
Date of Patent:
May. 10, 2011

Filed:

Mar. 25, 2009
Applicant:

Hongwei Wang, Fremont, CA (US);

Inventor:

Hongwei Wang, Fremont, CA (US);

Assignee:

Broadcom Corporation, Irvine, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H02H 3/22 (2006.01);
U.S. Cl.
CPC ...
Abstract

A system and method relieves ESD requirements on devices in circuits of chips that are susceptible to being damaged from ESD through an external pad. For example, one of the devices can be NMOS transistors having drains (or sources) connected to the external pad(s) and no (or significantly small) current flows from their drains (or sources) to the corresponding pad(s). In order to protect such a device, an ESD protecting system is coupled between the NMOS device and the pad. The ESD protecting system can include an n-type transistor or a p-type transistor.


Find Patent Forward Citations

Wang, Hongwei. (2011). System and method to relieve esd requirements of nmos transistors (U.S. Patent No. 7940501). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/7940501

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

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