The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Patent No.:

US 7940064 B1

PDF
Full Text
Expired
Date of Patent:
May. 10, 2011

Filed:

May. 29, 2006
Applicants:

Terutsugu Segawa, Osaka, JP;

Minoru Sanada, Osaka, JP;

Inventors:

Terutsugu Segawa, Osaka, JP;

Minoru Sanada, Osaka, JP;

Assignee:
Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
G01R 31/00 (2006.01);
U.S. Cl.
CPC ...
Abstract

A temperature regulation plateis divided into at least two areas, a heaterfor applying a temperature load in correspondence with such areas and its control system are divided and controlled independently to set temperatures, and a cooling source is controlled by comparing the measurements from temperature sensorsarranged in respective areas for controlling the heaterand switching the measurement for calculating the control output sequentially thus reducing variation in in-plane temperature of a wafer due to heating when an electric load is applied. Since consumption and burning of a probe are prevented, highly reliable wafer level burn-in method and apparatus can be provided.


Find Patent Forward Citations

Segawa, Terutsugu. (2011). Method and apparatus for wafer level burn-in (U.S. Patent No. 7940064). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/7940064

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