The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
May. 10, 2011

Filed:

Sep. 20, 2006
Applicants:

Hiroshi Osawa, Chiba, JP;

Takashi Hodota, Ichihara, JP;

Inventors:

Hiroshi Osawa, Chiba, JP;

Takashi Hodota, Ichihara, JP;

Assignee:

Showa Denko K.K., Tokyo, JP;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 33/00 (2010.01);
U.S. Cl.
CPC ...
Abstract

Disclosed is a semiconductor device which is improved in output power efficiency since reflection by the substrate is reduced. This semiconductor device is also excellent in strength characteristics of a supporting substrate. Also disclosed is a method for producing such a semiconductor device. Specifically disclosed is a nitride semiconductor device wherein at least an n-type semiconductor layer, a light-emitting layer, a p-type semiconductor layer, a metal film layer and a plated metal plate are sequentially stacked in this order on a substrate. This nitride semiconductor device is characterized in that the metal film layer and the plated metal plate are partially formed on the p-type semiconductor layer. Also disclosed is a nitride semiconductor device having a structure wherein at least an n-type semiconductor layer, a light-emitting layer, a p-type semiconductor layer, a metal film layer and a plated metal plate are sequentially stacked in this order, the device characterized in that the metal film layer and the plated metal plate are partially formed on the p-type semiconductor layer and a light-transmitting material layer is formed on the p-type semiconductor layer in a region where the metal film layer and the plated metal plate are not formed.


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