The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
May. 03, 2011

Filed:

Oct. 23, 2006
Applicants:

Hidetoshi Onodera, Otsu, JP;

Xuliang Zhang, Kitakyushu, JP;

Nobuto Ono, Sakura, JP;

Inventors:

Hidetoshi Onodera, Otsu, JP;

Xuliang Zhang, Kitakyushu, JP;

Nobuto Ono, Sakura, JP;

Assignees:
Attorneys:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
G06F 7/60 (2006.01); G06F 17/50 (2006.01); G06G 7/62 (2006.01); H01L 27/108 (2006.01); H01L 27/118 (2006.01);
U.S. Cl.
CPC ...
Abstract

A CMOS model generating apparatusaccording to the present invention generates a CMOS model by converting an I-Ispace into an x-xspace such that a typical condition TT and corner conditions FF, SS in the I-Ispace become (0, 0), (α, α) and (−α, −α) in the x-xspace, determining an ellipse fitting to the respective mappings of the corner conditions FF, SS, FS and SF with the mapping (0, 0) of the typical condition TT as a center, expressing two independent principal components in the form of a Gaussian distribution using the major and minor axes of this ellipse as axes of the principal components, and obtaining a probability distribution determining deviations of the Gaussian distribution such that the cumulative probability within this ellipse becomes equal to the one presumed by the corner conditions FF, SS, FS and SF.


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