The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
May. 03, 2011

Filed:

Nov. 09, 2007
Applicants:

Simon Pang, San Diego, CA (US);

Viet Linh DO, Carlsbad, CA (US);

Mehmet Mustafa Eker, San Marcos, CA (US);

Inventors:

Simon Pang, San Diego, CA (US);

Viet Linh Do, Carlsbad, CA (US);

Mehmet Mustafa Eker, San Marcos, CA (US);

Assignee:
Attorneys:
Primary Examiner:
Int. Cl.
CPC ...
H04L 7/00 (2006.01);
U.S. Cl.
CPC ...
Abstract

A system and method are provided for detecting a false clock frequency lock in a clock and data recovery (CDR) device. The method accepts a digital raw data signal at a first rate and counts edge transitions in the raw data signal, creating a raw count. A clock signal is also accepted at a second rate. The clock signal is a timing reference recovered from the raw data signal. The raw data signal is sampled at a rate responsive to the clock signal, generating a sampled signal. Edge transitions are counted in the sampled signal, creating a sampled count. Then, the raw count is compared to the sampled count, to determine if the first rate is equal to the second rate. The method is used to determine if the second rate is less than the first rate—to detect if the clock signal is incorrectly locked to the first rate.


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