The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
May. 03, 2011

Filed:

May. 26, 2009
Applicants:

Theodore S. Moise, Iv, Dallas, TX (US);

Scott R. Summerfelt, Garland, TX (US);

Kezhakkedath R. Udayakumar, Dallas, TX (US);

Inventors:

Theodore S. Moise, IV, Dallas, TX (US);

Scott R. Summerfelt, Garland, TX (US);

Kezhakkedath R. Udayakumar, Dallas, TX (US);

Assignee:
Attorneys:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L 21/00 (2006.01);
U.S. Cl.
CPC ...
Abstract

One aspect of the invention relates to a method of manufacturing an integrated circuit comprising forming an array of ferroelectric memory cells on a semiconductor substrate, heating the substrate to a temperature near a Curie temperature of the ferroelectric cores, and subjecting the substrate to a temperature program, whereby thermally induced stresses on the ferroelectric cores cause a switched polarization of the cores to increase by at least about 25% as the cores cool to about room temperature. Embodiments of the invention include metal filled vias of expanded cross-section above and below the ferroelectric cores, which increase the thermal stresses on the ferroelectric cores during cooling.


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