The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
May. 03, 2011

Filed:

Nov. 01, 2007
Applicants:

Scott Irving, Cape Elizabeth, ME (US);

Yong Liu, Scarborough, ME (US);

Timwah Luk, Falmouth, ME (US);

Inventors:

Scott Irving, Cape Elizabeth, ME (US);

Yong Liu, Scarborough, ME (US);

Timwah Luk, Falmouth, ME (US);

Assignee:

Fairchild Semiconductor Corporation, South Portland, ME (US);

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
G01N 3/00 (2006.01);
U.S. Cl.
CPC ...
Abstract

A chip with resistive, metallic strain gauges distributed on surfaces on and buried within the chip. Also, vertically arranged vias and vertical thin film resistive strain gauges are described. The resistive strain gauges can be multiplexed wherein strain can be measured across the topology of the chip in each of the top, bottom and buried layers and any vertical strain. The resistive strain gauges may be in serpentine patterns and may be arranged on via or on vertical edges of grooves that extend from an upper or lower surface of the chip to buried layers. In this fashion, the distributed strain gauges may be used to map the strain throughout the body of a chip. A Kelvin bridge may be used to measure the strain, but other such measuring techniques and devices may be used.


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