Preparing instruction groups for a processor having multiple issue ports

Abstract

During program code conversion, such as in a dynamic binary translator, automatic code generation provides target codeexecutable by a target processor. Multiple instruction portsdisperse a group of instructions to functional unitsof the processor Disclosed is a mechanism of preparing an instruction groupusing a plurality of poolshaving a hierarchical structure-. Each pool represents a different overlapping subset of the issue ports. Placing an instructioninto a particular poolalso reduces vacancies in any one or more subsidiary pools in the hierarchy. In a preferred embodiment, a counter valueis associated with each poolto track vacancies. A valid instruction groupis formed by picking the placed instructionsfrom the pools. The instruction groups are generated accurately and automatically. Decoding errors and stalls are minimized or completely avoided.