Master slave delay locked loops and uses thereof

Abstract

Various systems and methods for delaying a signal relative to another signal are disclosed. As one example, a delay lock loop circuit is disclosed that includes at least two delay stages. Each of the aforementioned delay stages include a plurality of selectable delay elements. Such selectable delay elements may be, but are not limited to, a plurality of single input buffers, and a plurality of multiple input logic gates. Further, a first of the delay stages is selectably driven by one of a first signal and a reference signal, and the stage provides a first stage output. A second of the delay stages is selectably driven by one of a second signal and the first stage output, and the stage provides a second stage output. The circuit further includes a mode signal that has at least two states. One of the two states causes the first signal to drive the first delay stage and the second signal to drive the second delay stage, and the other state causes the reference signal to drive the first delay stage and the first stage output to drive the second delay stage. In some cases, the first state is referred to as a slave state and the second state is referred to as a master state. In addition, the circuit includes a feedback loop.