The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Apr. 26, 2011

Filed:

Nov. 16, 2006
Applicants:

Toshihiko Maeda, Kirishima, JP;

Katsuyuki Yoshida, Kirishima, JP;

Kouzou Makinouchi, Satsumasendai, JP;

Inventors:

Toshihiko Maeda, Kirishima, JP;

Katsuyuki Yoshida, Kirishima, JP;

Kouzou Makinouchi, Satsumasendai, JP;

Assignee:

Kyocera Corporation, Kyoto, JP;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 23/48 (2006.01);
U.S. Cl.
CPC ...
Abstract

An electronic component sealing substrate capable of configuring an electronic apparatus in which the influence of electromagnetic coupling and radio frequency noises between an electrical connection path and a micro electronic mechanical system is suppressed is provided. An electronic component sealing substrate () for hermetically sealing a micro electronic mechanical system () of an electronic component () that includes a semiconductor substrate (), the micro electronic mechanical system () formed on a main face of the semiconductor substrate (), and an electrode () electrically connected to the micro electronic mechanical system (), includes an insulating substrate () that has a first main face joined to the main face of the semiconductor substrate () so as to hermetically seal the micro electronic mechanical system (), and a wiring conductor () that has an end extending to the first main face of the insulating substrate () and is electrically connected to the electrode () of the electronic component (), and the end of the wiring conductor () is positioned outside a joined portion of the main face of the semiconductor substrate () and the first main face of the insulating substrate ().


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