The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Apr. 26, 2011
Filed:
May. 19, 2009
Jae-hyun Park, Yongin-si, KR;
Jeong-uk Han, Suwon-si, KR;
Jae-min Yu, Seoul, KR;
Young-cheon Jeong, Yongin-si, KR;
Sang-hoon Park, Hwaseong-si, KR;
Kwan-jong Roh, Gunpo-si, KR;
Byeong-cheol Lim, Busan, KR;
Yong-seok Chung, Seoul, KR;
Jae-Hyun Park, Yongin-si, KR;
Jeong-Uk Han, Suwon-si, KR;
Jae-Min Yu, Seoul, KR;
Young-Cheon Jeong, Yongin-si, KR;
Sang-Hoon Park, Hwaseong-si, KR;
Kwan-Jong Roh, Gunpo-si, KR;
Byeong-Cheol Lim, Busan, KR;
Yong-Seok Chung, Seoul, KR;
Samsung Electronics Co., Ltd., Gyeonggi-do, KR;
Abstract
In a method of manufacturing a semiconductor device, a tunnel insulation layer is formed on a substrate. A charge trapping layer is formed on the tunnel insulation layer. A protection layer pattern or a mold is formed on the charge trapping layer. Charge trapping layer patterns are formed on the tunnel insulation layer by etching the charge trapping layer using the protection layer pattern or the mold. The charge trapping layer patterns may be spaced apart from each other. Blocking layers are formed on the charge trapping layer patterns, respectively. A gate electrode is formed on the blocking layers and the tunnel insulation layer using the protection layer pattern or the mold.