The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Apr. 26, 2011

Filed:

Mar. 15, 2007
Applicants:

Adrian I. Cogan, Redwood City, CA (US);

Jiyuan Luan, Fremont, CA (US);

Adrian Mikolajczak, Los Altos, CA (US);

Inventors:

Adrian I. Cogan, Redwood City, CA (US);

Jiyuan Luan, Fremont, CA (US);

Adrian Mikolajczak, Los Altos, CA (US);

Assignee:

Tyco Electronics Corporation, Berwyn, PA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 21/332 (2006.01);
U.S. Cl.
CPC ...
Abstract

A method for protecting a circuit from a high energy pulse includes placing a PPTC resistive element in series with the circuit and placing an energy pulse clamping semiconductor diode in shunt across the circuit and further includes forming the diode to have: a substrate with carriers of a first type of conductivity in a first, high concentration level (e.g. n++), a first major face and a second major face opposite to the first major face; a layer of semiconductor material having carriers of the first type of conductivity in a second concentration level lower than the first level (e.g. n+), and an outer surface; a region formed at an outer surface having carriers of a second type of conductivity in a third concentration level (e.g. p+); at least one cell having carriers of the second type of conductivity in a fourth concentration level greater than the third concentration level (e.g. p++); and, a cathode electrode and an anode electrode. In the method, the diode region becomes a second-level bi-directional intrinsic conduction region as an intrinsic temperature of the region is approached in response to thermal energy initially generated at the diode cell in response to the high energy electrical pulse. The method includes thermally coupling the diode to the PPTC resistive element to accelerate trip thereof in response to the high energy electrical pulse.


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