The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Apr. 19, 2011
Filed:
Sep. 09, 2008
Samuel I. Ward, Round Rock, TX (US);
Benjiman L. Goodman, Cedar Park, TX (US);
Joshua P. Hernandez, Paige, TX (US);
Linton B. Ward, Jr., Austin, TX (US);
Samuel I. Ward, Round Rock, TX (US);
Benjiman L. Goodman, Cedar Park, TX (US);
Joshua P. Hernandez, Paige, TX (US);
Linton B. Ward, Jr., Austin, TX (US);
International Business Machines Corporation, Armonk, NY (US);
Abstract
A system comprises a circuit analysis module configured to analyze a device under test (DUT), the DUT comprising a plurality of latches coupled together in a scan chain. The circuit analysis module analyzes a DUT for sub-circuits within the DUT and identifies a logical description of identified sub-circuits. A don't-care analysis module couples to the circuit analysis module identifies absolute don't-care latches associated with the identified sub-circuits. A sub-circuit exception module couples to the circuit analysis module and selects weighted input values for an identified sub-circuit, based on the identified absolute don't-care latches and the logical description of the identified sub-circuit. The sub-circuit exception module stores the selected weighted input values for the sub-circuit and associates the selected weighted input values with the logical description.