The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Apr. 19, 2011

Filed:

Jun. 30, 2005
Applicants:

Uri Shasha, Kiryat Ono, IL;

Sagi Gurfinkel, Austin, TX (US);

Gilad Hassid, Reshon Letzion, IL;

Eran Kahn, Tel-Aviv-Jaffa, IL;

Inventors:

Uri Shasha, Kiryat Ono, IL;

Sagi Gurfinkel, Austin, TX (US);

Gilad Hassid, Reshon Letzion, IL;

Eran Kahn, Tel-Aviv-Jaffa, IL;

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06F 13/28 (2006.01);
U.S. Cl.
CPC ...
Abstract

A method for controlling multiple DMA tasks, the method includes receiving multiple DMA task requests; the method is characterized by defining multiple buffer descriptors for each of a plurality of DMA channel; wherein at least two buffer descriptors comprise timing information that controls an execution of cyclic time based DMA tasks; selecting a DMA task request out of the multiple DMA task requests; executing a DMA task or a DMA task iteration and updating the buffer descriptor associated with the selected DMA task request to reflect the execution; and jumping to the stage of selecting. A device that includes a memory unit; the device is characterized by including a DMA controller that is adapted to: (i) access at least one buffer descriptor out of multiple buffer descriptors defined for each of a plurality of DMA channel, wherein at least two buffer descriptors comprise timing information that controls an execution of cyclic time based DMA tasks; (ii) receive multiple DMA task requests, (iii) select a DMA task request out of the multiple DMA task requests, and (iv) execute a DMA task or a DMA task iteration and update a buffer descriptor associated with the selected DMA task request to reflect the execution.


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