The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Apr. 19, 2011

Filed:

Aug. 01, 2008
Applicants:

Yong-ju Lee, DaeJeon, KR;

Ok-gee Min, DaeJeon, KR;

Chang-soo Kim, DaeJeon, KR;

Yoo-hyun Park, DaeJeon, KR;

Choon-seo Park, DaeJeon, KR;

Song-woo Sok, DaeJeon, KR;

Jin-hwan Jeong, Seoul, KR;

Won-jae Lee, DaeJeon, KR;

Hag-young Kim, DaeJeon, KR;

Inventors:

Yong-Ju Lee, DaeJeon, KR;

Ok-Gee Min, DaeJeon, KR;

Chang-Soo Kim, DaeJeon, KR;

Yoo-Hyun Park, DaeJeon, KR;

Choon-Seo Park, DaeJeon, KR;

Song-Woo Sok, DaeJeon, KR;

Jin-Hwan Jeong, Seoul, KR;

Won-Jae Lee, DaeJeon, KR;

Hag-Young Kim, DaeJeon, KR;

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
G06F 17/18 (2006.01);
U.S. Cl.
CPC ...
Abstract

Provided is an availability prediction method for a high availability. The method includes calculating a basic survival probability that the other node survives until a failure on one node of two nodes constituting a cluster is fixed, and determining an optimal number of nodes meeting a preset reference availability probability by calculating an availability probability for a predetermined range of the number of nodes on the basis of the basic survival probability. The method determines the number of nodes in the high availability cluster so as to match a reference availability probability, and is able to accomplish an optimal configuration of a cluster by calculating the availability probabilities for combinations between active node and passive nodes and between head nodes and switches.


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