The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Apr. 19, 2011
Filed:
Mar. 12, 2008
Vijay Kumar Srinivasa Raghavan, Colorado Springs, CO (US);
Leonard Gitlan, Colorado Springs, CO (US);
Vijay Kumar Srinivasa Raghavan, Colorado Springs, CO (US);
Leonard Gitlan, Colorado Springs, CO (US);
Cypress Semiconductor Corporation, San Jose, CA (US);
Abstract
A method of optimizing memory cell write/read is disclosed. The memory cell write/read is optimized by first reading the memory cell data using the normal mode. Next the page latch data that was used to NV (Non-Volatile) write the memory is also read back directly from the page latches. The two data are then compared to verify a successful and optimized memory cell write/read. NV writes and reads are performed with various high voltage parameters and sense amplifier reference settings to arrive at the most optimal one that gives the largest sense window for best write/read reliability. The page latch read mode is also used as a DFT (Design for Test) test mode to check for page latch functionality and page address uniqueness without having to write the memory cell. The page latch is written with logic data and read out directly using the page latch read mode to verify page functionality.