The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Apr. 12, 2011
Filed:
Jul. 07, 2006
Soorgoli Ashok Halambi, Bangalore, IN;
Sarang Ramchandra Shelke, Bangalore, IN;
Bhramar Bhushan Vatsa, Bangalore, IN;
Dibyapran Sanyal, Noida, IN;
Nishant Manohar Nakate, Bangalore, IN;
Ramanujan K Valmiki, Bangalore, IN;
Sai Pramod Kumar Atmakuru, Hyderabad, IN;
William C Salefski, San Jose, CA (US);
Vidya Praveen, Bangalore, IN;
Soorgoli Ashok Halambi, Bangalore, IN;
Sarang Ramchandra Shelke, Bangalore, IN;
Bhramar Bhushan Vatsa, Bangalore, IN;
Dibyapran Sanyal, Noida, IN;
Nishant Manohar Nakate, Bangalore, IN;
Ramanujan K Valmiki, Bangalore, IN;
Sai Pramod Kumar Atmakuru, Hyderabad, IN;
William C Salefski, San Jose, CA (US);
Vidya Praveen, Bangalore, IN;
Other;
Abstract
This invention describes a compilation method of extracting and implementing an accelerator control program from an application source code in a processor based system. The application source code comprises arrays and loops. The input application source code is sequential, with loop, branch and call control structures, while the generated output of this invention has parallel execution semantics. The compilation method comprises the step of performing loop nest analysis, transformations and backend processes. The step of loop nest analysis consists of dependence analysis and pointer analysis. Dependence analysis determines the conflicts between the various references to arrays in the loop, and pointer analysis determines if two pointer references in a loop are in conflict. Transformations convert the loops from their original sequential execution semantics to parallel execution semantics. The back-end process determines the parameters and memory map of the accelerator and the hardware dependent software.