The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Apr. 12, 2011
Filed:
Sep. 09, 2008
Samuel I. Ward, Round Rock, TX (US);
Benjiman L. Goodman, Cedar Park, TX (US);
Joshua P. Hernandez, Paige, TX (US);
Linton B. Ward, Jr., Austin, TX (US);
Samuel I. Ward, Round Rock, TX (US);
Benjiman L. Goodman, Cedar Park, TX (US);
Joshua P. Hernandez, Paige, TX (US);
Linton B. Ward, Jr., Austin, TX (US);
International Business Machines Corporation, Armonk, NY (US);
Abstract
A system comprises a circuit analysis module configured to analyze a device under test (DUT), the DUT comprising a plurality of latches coupled together in a scan chain. A don't-care analysis module identifies absolute don't-care latches within the DUT, assigns a weighted value to the bit positions of identified don't-care latches, and identifies absolute don't-care bits within a general test pattern. The circuit analysis module replaces identified absolute don't-care bits in the general test pattern according to the weighted value of the associated bit position, generating a weighted test pattern. A test vector module generates a test vector based on the weighted test pattern and an input module applies the test vector to the DUT.