The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Apr. 12, 2011
Filed:
Jan. 07, 2008
Joel T. Irby, Austin, TX (US);
Grady L. Giles, Dripping Springs, TX (US);
Alexander W. Schaefer, Austin, TX (US);
Gregory A. Constant, Austin, TX (US);
Floyd L. Dankert, Austin, TX (US);
Amy M. Novak, Austin, TX (US);
Joel T. Irby, Austin, TX (US);
Grady L. Giles, Dripping Springs, TX (US);
Alexander W. Schaefer, Austin, TX (US);
Gregory A. Constant, Austin, TX (US);
Floyd L. Dankert, Austin, TX (US);
Amy M. Novak, Austin, TX (US);
Advanced Micro Devices, Inc., Sunnyvale, CA (US);
Abstract
An integrated circuit. The integrated circuit includes a plurality of logic circuits. The integrated circuit further includes a scan chain including a plurality of scan elements coupled in series, wherein the scan chain is configured to load stimulus data to be applied to the logic circuits for testing. The scan chain is further configured to capture data subsequent to applying the stimulus data. The integrated circuit also includes an embedded memory having a read port, wherein the read port is coupled to one or more of the plurality of logic circuits via a read path. The embedded memory includes a virtual entry having a plurality of scan-controllable storage elements. During testing, the virtual entry is operable to apply transition data to the read path in order to cause logic state transitions in the one or more logic circuits in the read path.