Method and apparatus for adjusting timing signal between media controller and storage media

Abstract

A storage system controller () includes a plurality of media controllers (), a local microprocessor (), and a host interface logic (), operably coupled by a multi-drop bus. The multi-drop bus includes a control bus (), a payload data bus (), a real-time ready-status (data ready) signaling bus () and a general microprocessor bus (). Each media controller has a storage media () operably coupled thereto. Each media controller includes a parameter storage (), a media interface circuit (), a control data state machine (), a command sequencer state machine (), a media-side multi-mode transfer state machine (), a dual-port memory (), a memory controller (), and a host-side transfer state machine (). The host interface logic and the media controllers are implemented in one or more Field Programmable Gate Arrays. The storage system architecture allows the microprocessor to simultaneously broadcast a command to the media controllers, which have a capability to substantially simultaneously begin exchanging data with the storage media in response to the command. The storage system has provision for Redundant Array of Independent Disks, method 0, operation.