Automatic clock and data alignment

Abstract

A circuit is described for automatically adjusting a phase of an input register load clock to be synchronized with transitions of data bits forming an n-bit word. The circuit detects the first transition of a data bit in the n-bit word. The circuit then time-shifts the input clock, to generate a shifted clock, so that a triggering edge of the shifted clock occurs sometime after generation of the transition detect signal, such as in the middle third of a data cycle. Shifting the input clock may be performed by multiplying the input clock to generate a plurality of sub-clock cycles and selecting one of the sub-clock cycles as the start of the shifted clock cycle. The parallel data are applied to inputs of input registers clocked using the shifted clock as the load clock. Thus, the load clock occurs at an optimum time near the middle of a data cycle.