The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Apr. 05, 2011

Filed:

Apr. 30, 2010
Applicants:

Tomoyuki Arai, Kawasaki, JP;

Masahiro Kudo, Kawasaki, JP;

Inventors:

Tomoyuki Arai, Kawasaki, JP;

Masahiro Kudo, Kawasaki, JP;

Assignee:

Fujitsu Limited, Kawasaki, JP;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H03F 3/04 (2006.01);
U.S. Cl.
CPC ...
Abstract

A bias circuit for applying a bias voltage to a nonlinear amplification circuit, including a constant-current source; and a first, second, third, and fourth transistors, wherein a current mirror circuit is configured by the first transistor and the second transistor, and the bias voltage is outputted from the drain of the second transistor, gate lengths and gate widths of the first and second transistor are the same, gate lengths of the first to fourth transistor are the same, and gate lengths and gate widths of the first, second, third, and fourth transistor are configured so that k−kis approximately 1, where kstands for a ratio of a gate width of the third transistor to the gate width of the first transistor and kstands for a ratio of a gate width of the fourth transistor to the gate width of the first transistor.


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