The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Apr. 05, 2011

Filed:

Oct. 16, 2009
Applicants:

Jin-yong OH, Hwaseong-si, KR;

Sang-youn JO, Suwon-si, KR;

Joon-hee Lee, Seongnam-si, KR;

Jae-sun Yun, Anyang-si, KR;

Seong-soo Kim, Hwaseong-si, KR;

Inventors:

Jin-Yong Oh, Hwaseong-si, KR;

Sang-youn Jo, Suwon-si, KR;

Joon-hee Lee, Seongnam-si, KR;

Jae-sun Yun, Anyang-si, KR;

Seong-soo Kim, Hwaseong-si, KR;

Assignee:

Samsung Electronics Co., Ltd., Suwon-si, Gyeonggi-do, KR;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 25/00 (2006.01);
U.S. Cl.
CPC ...
Abstract

A method of applying a wire voltage to a semiconductor device including a plurality of active regions and a field region insulating the plurality of active regions, wherein the field region includes a plurality of wires. The method includes applying an operating voltage required for an operation of the semiconductor device to at least one of the plurality of wires, and applying a voltage lower than the operating voltage to a wire adjacent to at least one of the plurality of active regions from among the plurality of wires. Thus, leakage current caused by an imaginary parasitic transistor due to a wire of the field region may be prevented.


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