The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Apr. 05, 2011
Filed:
Sep. 25, 2008
Raymond A. Bertram, Austin, TX (US);
Mark J. Brazell, Cedar Park, TX (US);
Vanessa S. Canac, Austin, TX (US);
Darius D. Gaskins, Austin, TX (US);
James R. Lundberg, Austin, TX (US);
Matthew Russell Nixon, Austin, TX (US);
Raymond A. Bertram, Austin, TX (US);
Mark J. Brazell, Cedar Park, TX (US);
Vanessa S. Canac, Austin, TX (US);
Darius D. Gaskins, Austin, TX (US);
James R. Lundberg, Austin, TX (US);
Matthew Russell Nixon, Austin, TX (US);
VIA Technologies, Inc., New Taipei, TW;
Abstract
A microprocessor including a substrate bias rail providing a bias voltage during a first operating mode, a supply node providing a core voltage, a clamp device coupled between the bias rail and the supply node, and control logic. The control logic turns on the clamp device to clamp the bias rail to the supply node during a second operating mode and turns off the clamp device during the first operating mode. The clamp devices may be implemented with P-channel and N-channel devices. Level shift and buffer circuits may be provided to control the clamp devices based on substrate bias voltage levels. The microprocessor may include a substrate with first and second areas each including separate substrate bias rails. The control logic separately turns on and off clamp devices to selectively clamp the substrate bias rails in the first and second areas based on various power modes.