The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Apr. 05, 2011
Filed:
Dec. 01, 2006
Kevin Horn, Brighton, CO (US);
Forest Dillinger, Golden, CO (US);
Otto Richard Buhler, Boulder, CO (US);
Karl Sauter, Pleasanton, CA (US);
Kevin Horn, Brighton, CO (US);
Forest Dillinger, Golden, CO (US);
Otto Richard Buhler, Boulder, CO (US);
Karl Sauter, Pleasanton, CA (US);
Oracle America, Inc., Redwood City, CA (US);
Abstract
An improved technique for power distribution for use by high speed integrated circuit devices. A mixture of high dielectric constant, Er and low Er materials are used in a dielectric layer sandwiched between the voltage and ground planes of a printed circuit board that is used to fixture one or more integrated circuit devices. The low Er material is used in an area contained by the location of the integrated circuit device and its corresponding decoupling capacitors located nearby. High Er material is used in areas between the regions of low Er material. The low Er material improves that speed at which current from an adjoining decoupling capacitor can propagate to a power pin of the integrated circuit device. The high Er material mitigates cross-coupling of noise between the low Er regions.