Semiconductor memory device that is resistant to high voltages and a method of manufacturing the same

Abstract

A semiconductor memory device having a memory cell region and a peripheral circuit region, and a method of manufacturing such a semiconductor memory device, are proposed, in which trench grooves are formed to be shallow in the memory cell region in order to improve the yield, and trench grooves are formed to be deep in the high voltage transistor region of the peripheral circuit region, in particular in a high voltage transistor region thereof, in order to improve the element isolation withstand voltage. A plurality of memory cell transistors having an ONO layerserving as a charge accumulating insulating layer are provided in the memory cell region, where element isolation groovesfor these memory cell transistors are narrow and shallow. Two types of transistors, one for high voltage and the other for low voltage, having gate insulating layersor, which are different from the ONO layerin the memory cell region, are provided in the peripheral circuit region, where at least element isolation groovesfor high voltage transistors are wide and deep. In this way, it is possible to improve the degree of integration and yield in the memory cell region, and secure withstand voltage in the peripheral circuit region.