The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Mar. 29, 2011
Filed:
Mar. 15, 2007
Applicants:
Hsi-chuan Chen, Fremont, CA (US);
Chih-liang Cheng, Fremont, CA (US);
Chung-do Yang, Saratoga, CA (US);
Jeong-tyng LI, Cupertino, CA (US);
Inventors:
Hsi-Chuan Chen, Fremont, CA (US);
Chih-Liang Cheng, Fremont, CA (US);
Chung-Do Yang, Saratoga, CA (US);
Jeong-Tyng Li, Cupertino, CA (US);
Assignee:
SpringSoft USA, Inc., San Jose, CA (US);
Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
G06F 17/50 (2006.01);
U.S. Cl.
CPC ...
Abstract
Improving the timing and/or yield of a circuit design is disclosed. Timing and yield improvements are often competing objectives in circuit design since timing improvements typically result from reducing capacitive couplings and yield improvements typically increase capacitive couplings. Trade-offs between timing and yield improvements are consequently part of the circuit design and/or optimization process.