The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Mar. 29, 2011
Filed:
Dec. 04, 2006
Reuven Elhamias, Sunnyvale, CA (US);
David Zehavi, Newe Ziv, IL;
Roni Barzilai, Cfar-Vradim, IL;
Vivek Mani, Chicago, IL (US);
Simon Stolero, Nahriya, IL;
Reuven Elhamias, Sunnyvale, CA (US);
David Zehavi, Newe Ziv, IL;
Roni Barzilai, Cfar-Vradim, IL;
Vivek Mani, Chicago, IL (US);
Simon Stolero, Nahriya, IL;
SanDisk Corporation, Milpitas, CA (US);
Abstract
Methods and systems for working around the timeout limitations of physical interface standards for detachable modules. By use of dummy data blocks to keep the bus active, the bus timeout requirements (in either direction) can be spoofed, to thereby permit more complex processing operations to be performed that may exceed the bus timeout of a particular specification. A controller in the memory system deasserts the ready signal and holds the bus connecting the computer system in a 'busy' state until the memory system is about to timeout. During a write operation, the controller receives dummy data blocks from the computer system before the write bus timeout period expires, causing the bus timeout period to be reset. During a read operation, the controller sends dummy data blocks to the computer system before the read bus timeout period expires, causing the bus timeout period to be reset.