The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Mar. 29, 2011
Filed:
May. 30, 2008
David W. Boerstler, Round Rock, TX (US);
Eskinder Hailu, Sunnyvale, CA (US);
Masaaki Kaneko, Round Rock, TX (US);
Jieming Qi, Austin, TX (US);
Bin Wan, Pittsburgh, PA (US);
David W. Boerstler, Round Rock, TX (US);
Eskinder Hailu, Sunnyvale, CA (US);
Masaaki Kaneko, Round Rock, TX (US);
Jieming Qi, Austin, TX (US);
Bin Wan, Pittsburgh, PA (US);
International Business Machines Corporation, Armonk, NY (US);
Abstract
A design structure for a circuit for measuring the absolute duty cycle of a signal anywhere on an integrated circuit device is provided. The circuit has a plurality of substantially identical pulse shaper elements, each of which expand the pulse of an input signal whose duty cycle is to be measured by a same amount. The outputs of the pulse shaper elements may be coupled to substantially identical divider circuits whose outputs are coupled to a multiplexer that selects two inputs for output to a set of master/slave configured flip-flops, one input serving as a clock and the other as data to the flip-flops. The flip-flops sample the divider outputs selected by the multiplexer to detect if the dividers have failed or not. The outputs of the flip-flops are provided to an XOR gate which outputs a duty cycle signal indicative of the duty cycle of the input signal.