The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Mar. 29, 2011
Filed:
Dec. 11, 2008
Norihide Kinugasa, Kyoto, JP;
Mitsuhiko Otani, Hyogo, JP;
Naohisa Hatani, Kyoto, JP;
Takayasu Kitou, Osaka, JP;
Norihide Kinugasa, Kyoto, JP;
Mitsuhiko Otani, Hyogo, JP;
Naohisa Hatani, Kyoto, JP;
Takayasu Kitou, Osaka, JP;
Panasonic Corporation, Osaka, JP;
Abstract
A variable delay circuit successively delays an input clock to generate a plurality of delayed clocks having different phases. A phase comparison circuit receives a first reference clock, which is either one of the delayed clocks or the input clock, and a second reference clock, which is one of the delayed clocks and whose phase lags behind that of the first reference clock, specifies a validated interval for the second reference clock, and compares the phases of the first and second reference clocks according to voltage levels of the first and second reference clocks only during the validated interval. A delay control circuit controls a delay time in the variable delay circuit according to a result of the comparison obtained by the phase comparison circuit.