The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Mar. 29, 2011
Filed:
Oct. 24, 2007
David Cecil Hays, Niskayuna, NY (US);
Marco Francesco Aimi, Niskayuna, NY (US);
Christopher Fred Keimel, Schenectady, NY (US);
Glenn Scott Claydon, Wynantskill, NY (US);
Kanakasabapathi Subramanian, Clifton Park, NY (US);
Oliver Charles Boomhower, Waterford, NY (US);
David Cecil Hays, Niskayuna, NY (US);
Marco Francesco Aimi, Niskayuna, NY (US);
Christopher Fred Keimel, Schenectady, NY (US);
Glenn Scott Claydon, Wynantskill, NY (US);
Kanakasabapathi Subramanian, Clifton Park, NY (US);
Oliver Charles Boomhower, Waterford, NY (US);
General Electric Company, Niskayuna, NY (US);
Abstract
An electrical through-connection, or via, that passes through a substrate to a bus on a first surface of the substrate. The via may be configured with an interlock such that the electrically conductive core of the via is constrained to thermally expand towards the second surface, away from the bus, thus preventing damage to the bus. The interlock may be a local constriction or enlargement of the via near the first surface of the substrate. The via may be greater in length along the bus than a unit spacing of beams in a parallel microswitch array actuated in unison along the bus. The via may be narrower in width than in length, and may form a trapezoidal geometry that is larger at the second surface of the substrate than at the first surface.