The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Mar. 29, 2011
Filed:
Apr. 29, 2009
Jung-woo Park, Icheon-si, KR;
Jin-ki Jung, Icheon-si, KR;
Kwon Hong, Icheon-si, KR;
Ki-seon Park, Icheon-si, KR;
Jung-Woo Park, Icheon-si, KR;
Jin-Ki Jung, Icheon-si, KR;
Kwon Hong, Icheon-si, KR;
Ki-Seon Park, Icheon-si, KR;
Hynix Semiconductor Inc., Icheon-si, Gyeonggi-do, KR;
Abstract
Provided is a method of fabricating a non-volatile semiconductor device. The method includes: forming a first hard mask layer over a substrate; etching the first hard mask layer and the substrate to form a plurality of isolation trenches extending in parallel to one another in a first direction; burying a dielectric layer in the isolation trenches to form a isolation layer; forming a plurality of floating gate mask patterns extending in parallel to one another in a second direction intersecting with the first direction over a resulting structure where the isolation layer is formed; etching the first hard mask layer by using the floating gate mask patterns as an etch barrier to form a plurality of island-shaped floating gate electrode trenches; and burying a conductive layer in the floating gate electrode trenches to form a plurality of island-shaped floating gate electrodes.