The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Mar. 29, 2011

Filed:

Mar. 19, 2008
Applicants:

Tsuyoshi Ogawa, Kanagawa, JP;

Hirokazu Nakayama, Kanagawa, JP;

Hirohito Miyazaki, Kanagawa, JP;

Namiko Takeshima, Kanagawa, JP;

Inventors:

Tsuyoshi Ogawa, Kanagawa, JP;

Hirokazu Nakayama, Kanagawa, JP;

Hirohito Miyazaki, Kanagawa, JP;

Namiko Takeshima, Kanagawa, JP;

Assignee:

Sony Corporation, Tokyo, JP;

Attorneys:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L 21/00 (2006.01);
U.S. Cl.
CPC ...
Abstract

A hybrid module includes a silicon substrate having a plurality of part mounting openings formed therein, the plurality of part mounting openings composed of through holes, a plurality of mounted parts that are mounted in the part mounting openings such that input/output portion forming surfaces are substantially flush with a first main surface of the silicon substrate, a sealing layer that is formed of a sealing material filled into the part mounting openings and covers the mounted parts, with the input/output portion forming surfaces exposed from the first main surface of the silicon substrate, to fix the mounted parts in the part mounting openings, and a wiring layer that is formed on the first main surface of the silicon substrate, and has a wiring pattern connected to input/output portions that are provided on the input/output portion forming surfaces of the mounted parts exposed from the first main surface.


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