The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Mar. 22, 2011

Filed:

Oct. 19, 2007
Applicants:

Hirofumi Miyashita, Osaka, JP;

Chie Kabuo, Kyoto, JP;

Nobuyuki Iwauchi, Kyoto, JP;

Yoichi Matsumura, Kyoto, JP;

Fumihiro Kimura, Kyoto, JP;

Tatsuo Gou, Kyoto, JP;

Yukiji Hashimoto, Kyoto, JP;

Inventors:

Hirofumi Miyashita, Osaka, JP;

Chie Kabuo, Kyoto, JP;

Nobuyuki Iwauchi, Kyoto, JP;

Yoichi Matsumura, Kyoto, JP;

Fumihiro Kimura, Kyoto, JP;

Tatsuo Gou, Kyoto, JP;

Yukiji Hashimoto, Kyoto, JP;

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06F 17/50 (2006.01);
U.S. Cl.
CPC ...
Abstract

A method for designing an interconnect structure of an interconnect layer in a semiconductor integrated circuit device includes the steps of: (a) inputting layout data of the semiconductor integrated circuit device; (b) controlling an air gap exclusion area based interconnects in the layout data; and (c) outputting layout data including the air gap exclusion area determined in the step (b).


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