The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Mar. 22, 2011

Filed:

Jan. 04, 2007
Applicants:

Sang-ho Park, Gunpo-si, KR;

Jong-bae Lee, Yongin-si, KR;

Moon-hyun Yoo, Suwon-si, KR;

Ho Shim, Suwon-si, KR;

Jin-won Kim, Yongin-si, KR;

Inventors:

Sang-ho Park, Gunpo-si, KR;

Jong-bae Lee, Yongin-si, KR;

Moon-hyun Yoo, Suwon-si, KR;

Ho Shim, Suwon-si, KR;

Jin-won Kim, Yongin-si, KR;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06F 17/50 (2006.01); G06F 9/455 (2006.01); G06F 11/22 (2006.01);
U.S. Cl.
CPC ...
Abstract

A method and an apparatus for verifying a logic circuit, capable of quicker operation, being applied to a logic gate-level or transistor-level circuit design, and verifying timing and analog signal characteristics of a signal. The logic circuit verification method includes a wave file generation stage and a logic circuit verification stage. The wave file generation stage generates a wave file that includes the waveforms of all nodes of the logic circuit using a design source file of the logic circuit. The stage of verification of the logic circuit verifies the logic circuit using a design reference file, which includes ideal operations of all the nodes of the logic circuit, and the wave file.


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