The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Mar. 22, 2011
Filed:
Oct. 16, 2008
Atsushi Masuda, Yokohama, JP;
Atsushi Masuda, Yokohama, JP;
Kabushiki Kaisha Toshiba, Tokyo, JP;
Abstract
A high-level synthesis apparatus for automatically generating a register transfer level (RTL) logic circuit from a behavioral description has a scheduling unit configured to perform data flow analysis and scheduling to generate a data flow graph showing an operation cycle of an operation from the behavioral description, a scheduling result inputting/outputting unit configured to extract a point to be allocated to a register from the data flow graph and output register information indicating the point, the scheduling result inputting/outputting unit being provided with dynamic analysis data that includes at least one of the number of times that data at the point has been substituted and the number of times that a value stored at the point has changed by a predetermined simulation, an allocating unit configured to consult dynamic analysis data and allocate circuit elements to the behavioral description, and an RTL description generating unit configured to generate the logic circuit based on the allocation of circuit elements by the allocating unit.