The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Mar. 22, 2011
Filed:
Mar. 21, 2008
Tilman Gloekler, Guertringen, DE;
Michael Kugel, Boeblingen, DE;
Thuyen Le, Taufkirchen, DE;
Matthias Woehrle, Bietigheim-Bissingen, DE;
Tilman Gloekler, Guertringen, DE;
Michael Kugel, Boeblingen, DE;
Thuyen Le, Taufkirchen, DE;
Matthias Woehrle, Bietigheim-Bissingen, DE;
International Business Machines Corporation, Armonk, NY (US);
Abstract
The present invention relates to a method for performing a logic built-in self-test (LBIST) on an electronic circuit with a plurality of logic circuits () and storage elements () connected serially to a number of LBIST stumps () between a pseudo-random-pattern generator () and a multiple-input-signature register (), wherein at least one constrained logic circuit () requires constrained values as input signals. Said method comprises the following steps: scanning the LBIST stumps () with the pseudo-random-pattern generator (), deactivating the multiple-input-signature register (), performing a functional update in order to propagate legal values into those storage elements (), which require constrained values, activating or resetting () the multiple-input-signature register (), and setting or programming a start value in a counter () for activating a loop back circuit () in order to avoid an overwriting of the well-constrained values in the storage elements ().