Scan chain cell with delay testing capability

Abstract

A scan chain cellis provided with a built-in delay testing capability. An invertergenerates an inverted form of the cell output which is available within the scan chain cellfor rapid use in forming a transition at the cell output Q. Clock gating circuitryis responsive to a hold signal to block the functional paththrough the scan chain cell and hold the output signal when desired. The functional clock clk may be clocked twice at speed to trigger capture of the results of processing the output of the scan chain cellfor the non-inverted value followed by the (internally generated) inverted value, i.e. a signal transition. In this way delay testing of the functional circuitrycan be performed.