The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Mar. 22, 2011
Filed:
Sep. 11, 2007
Yuta Tachibana, Toyokawa, JP;
Katsunori Takahashi, Hino, JP;
Toru Kasamatsu, Toyokawa, JP;
Tomonobu Tamura, Toyokawa, JP;
Norihiko Nakano, Hoi-gun, JP;
Yuta Tachibana, Toyokawa, JP;
Katsunori Takahashi, Hino, JP;
Toru Kasamatsu, Toyokawa, JP;
Tomonobu Tamura, Toyokawa, JP;
Norihiko Nakano, Hoi-gun, JP;
Konica Minolta Business Technologies, Inc., Tokyo, JP;
Abstract
A variable frequency clock output circuit, comprising: a target value register which stores a target value corresponding to an arbitrarily set target frequency; an increase/decrease value register which stores an arbitrarily set increase/decrease value; an adder-subtractor which has an input portion into which a current output value is inputted and outputs a calculation result obtained by adding/subtracting the increase/decrease value stored in the increase/decrease value register to/from the current output value inputted into the input portion based on an addition/subtraction instruction signal; a comparator which compares an output value of the adder-subtractor to the target value stored in the target value register, and outputs an addition/subtraction instruction signal to the adder-subtractor until the output value of the adder-subtractor and the target value coincide; and a clock generator which outputs a clock signal having a frequency proportional to the output value of the adder-subtractor.