Synchronization device and semiconductor device

Abstract

An apparatus for performing a channel-to-channel delay correction and frame synchronization with low latency includes, on each of a plurality of channels, a clock-and-data recovery circuit, a frequency divider circuit, a circuit for detecting the phase difference between the phase of the frequency-divided clock signal and the phase of a clock signal, a serial-to-parallel converter circuit, a register array for holding the parallel output of the serial-to-parallel converter circuit, and a frame-head detector for detecting a frame head from the output of the register array and outputting a frame detection signal. A last-frame-head detector receives the frame detection signals from each of the channels and detects a channel on which the frame head was detected last. The frame head detected last, the phase of the internal clock signal, and the phase of a frequency-divided clock of a retiming clock of the channel are adjusted to substantially coincide.