Integrated circuits with clearable memory elements

Abstract

Integrated circuits are provided that have memory elements. The memory elements may be organized in an array. Data such as programmable logic device configuration data may be loaded into the array using read and write control circuitry. Each memory element may store data using a pair of cross-coupled inverters. Power supply circuitry may be used to power the cross-coupled inverters. A positive power supply signal and a ground power supply signal may be provided to the inverters by the power supply circuitry. Each memory element may have an associated clear transistor. A clear control signal may be asserted to turn on the clear transistor when clearing the memory elements. A given one of the inverters in each memory element may be momentarily weakened with respect to the clear transistor in that memory element by using the power supply circuitry to temporarily elevate the ground power supply signal.