The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Mar. 22, 2011
Filed:
Dec. 08, 2009
Byoung Gon Yu, Daejeon, KR;
Yong-joo Kim, Uiwang, KR;
Sung Min Yoon, Daejeon, KR;
Seung-yun Lee, Daejeon, KR;
Young Sam Park, Daejeon, KR;
Soonwon Jung, Daejeon, KR;
Byoung Gon Yu, Daejeon, KR;
Yong-Joo Kim, Uiwang, KR;
Sung Min Yoon, Daejeon, KR;
Seung-Yun Lee, Daejeon, KR;
Young Sam Park, Daejeon, KR;
Soonwon Jung, Daejeon, KR;
Electronics and Telecommunications Research Institute, Daejeon, KR;
Abstract
Provided is a programmable logic block of a field-programmable gate array (FPGA). The programmable logic block includes a pull-up access transistor connected to a power source, an up-phase-change memory device connected to the pull-up access transistor, a down-phase-change memory device connected to the up-phase-change memory device, an output terminal between the up-phase-change memory device and the down-phase-change memory device, and a pull-down access transistor connected to the down-phase-change memory device and a ground. The resistance values of the up-phase-change memory device and the down-phase-change memory device are individually programmed.
Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile