Tolerant buffer circuit and interface

Abstract

The tolerant buffer circuit and interface are provided in which reverse inflow of current to a power supply voltage from an output terminal does not occur, even if the output terminal is at a higher potential than an output circuit power supply voltage during open-drain operation in an output circuit of a semiconductor integrated circuit, or if the output circuit power supply voltage becomes 0 V. A tolerant buffer circuit is provided with first and second PMOS transistors that are connected in series and that share a source between a power supply terminal and an output terminal, an NMOS transistor connected between the output terminal and a ground terminal, a first inverter output-connected to the gate of the first PMOS transistor, a second inverter output-connected to the gate of the second PMOS transistor, and a control circuit that outputs first, second, and third control signals to the first PMOS transistor, the second PMOS transistor, and the NMOS transistor, respectively, and controls the on/off state of these MOS transistors.