The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Mar. 15, 2011
Filed:
Feb. 27, 2007
Richard Meade, San Francisco, CA (US);
Sherif Eid, Sunnyvale, CA (US);
Lance Stevens, Burnsville, MN (US);
Miroslav Slanina, Sunnyvale, CA (US);
Richard Meade, San Francisco, CA (US);
Sherif Eid, Sunnyvale, CA (US);
Lance Stevens, Burnsville, MN (US);
Miroslav Slanina, Sunnyvale, CA (US);
Cypress Semiconductor Corporation, San Jose, CA (US);
Abstract
An apparatus and method are provided for testing a semiconductor device (DUT). Generally, the apparatus includes an interface board with conductive elements adapted to electrically couple with the DUT and connected to a number of test circuits. Each test circuit resides on one of a number of daughter cards on the interface board, and provides test input signals to and receives output signals from the DUT to generate a result based on a program loaded to the daughter cards before testing begins. The apparatus further includes a controller to drive the interface board and store test results. In one embodiment, the interface board is a load board for back end testing. In another embodiment, the interface board is a probe card for front end testing. Preferably, the apparatus is capable of testing DUTs including memory arrays, logic circuits or both, and the daughter cards are capable of being re-programmed and re-used on different DUTs.