The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Mar. 08, 2011
Filed:
Dec. 18, 2007
Kathleen C. Yu, Austin, TX (US);
Scott D. Hector, Austin, TX (US);
Robert L. Maziasz, Austin, TX (US);
Claudia A. Stanley, Austin, TX (US);
James E. Vasck, Austin, TX (US);
Kathleen C. Yu, Austin, TX (US);
Scott D. Hector, Austin, TX (US);
Robert L. Maziasz, Austin, TX (US);
Claudia A. Stanley, Austin, TX (US);
James E. Vasck, Austin, TX (US);
Freescale Semiconductor, Inc., Austin, TX (US);
Abstract
A method of area compaction for integrated circuit layout design comprises determining physical extent boundaries for each layer of at least first circuit and second circuit building blocks. Determining physical extent boundaries includes determining for each respective layer of the first circuit and second circuit building blocks (i) a used portion and (ii) a free portion. The used portion corresponds to a functional portion of the respective circuit building block and the free portion corresponds to a non-functional portion of the respective circuit building block. The method further includes establishing packing keys with respect to the determined physical extent boundaries of each layer of the first circuit and second circuit building blocks, respectively. The packing keys define an interlocking characteristic for packing compaction of the corresponding first circuit or second circuit building block with another circuit building block.