Branching memory-bus module with multiple downlink ports to standard fully-buffered memory modules

Abstract

A branching memory-bus module has one uplink port and two or more downlink ports. Frames sent downstream by a host processor are received on the uplink port and repeated to the multiple downlink ports to two or more branches of memory modules. Frames sent upstream to the processor by a memory module on a downlink port are repeated to the uplink port. A branching Advanced Memory Buffer (AMB) on the branching memory-bus module has re-timing and re-synchronizing buffers that repeat frames to the multiple downlink ports. Elastic buffers can merge and synchronize frames from different downlink branches. Separate northbound and southbound lanes may be replaced by bidirectional lanes to reduce pin counts. Latency from the host processor to the farthest memory module is reduced by branching compared with a serial daisy-chain of fully-buffered memory modules. Point-to-point bus segments have only two endpoints despite branching by the branching AMB.