Adjustment of divided clock in disk head read circuit

Abstract

A read circuit for providing multi-bit disk data to a disk controller in correspondence to analog data from a disk head, includes a low frequency clock generator whose phase is adjustable in response to a detection of the synchronization marker in the analog disk data. A high frequency clock is phase-locked to the output of the disk head, and synchronizes operation of an A/D converter and a bit detector which produces a verified single-bit based on the A/D output. A serial-to-parallel converter converts the single bit output from the bit detector to a parallel output, and the parallel output is latched to multi-bit disk data for use by the disk controller in accordance with a low frequency clock. The low frequency clock is generated by a clock generator from the high frequency clock with a phase that is adjustable in response to the synchronization mark detector.