The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Mar. 08, 2011
Filed:
Mar. 12, 2008
Mamdouh Yanni, Kitchener, CA;
Mamdouh Yanni, Kitchener, CA;
Research In Motion Limited, Waterloo, Ontario, CA;
Abstract
A system and method of providing a clock signal to a navigation satellite receiver in a device is disclosed. A clock signal generated by a voltage controlled temperature compensated crystal oscillator (VCTCXO) in a cellular engine of the same device is appropriated to clock a numerically controlled oscillator (NCO) programmed to generate an adjusted clock signal suitable for use in receiving signals from navigation satellites and to heterodyne them down to baseband or an intermediate frequency for processing. Preferably, if the cellular engine has an automatic frequency control (AFC) module for adjusting the voltage control input to the VCTCXO to compensate for a change in the operating environment of the cellular engine, the AFC module modifies the control word in the NCO to counteract such adjustment so that the adjusted clock signal provided to the navigation satellite receiver is not unduly impacted. The use of the NCO ensures that the adjusted clock signal remains phase continuous throughout any such adjustments, so that positional lock of the navigation satellite receiver should not be lost. The sharing of the VCTCXO by the cellular engine and the navigation satellite receiver results in component cost and board space savings, economy in power consumption and reduced engineering effort in routing clock signals throughout the circuit board.