The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Mar. 08, 2011
Filed:
Aug. 27, 2008
Cameron Patterson, Blacksburg, VA (US);
Peter Athanas, Newport, VA (US);
John K. Bowen, Alexandria, VA (US);
Timothy G. Dunham, Roanoke, VA (US);
Justin D. Rice, Coral Springs, FL (US);
Matthew T. Shelburne, Christiansburg, VA (US);
Jorge A. Suris Pletri, Blacksburg, VA (US);
Jonathan Graf, Blacksburg, VA (US);
Cameron Patterson, Blacksburg, VA (US);
Peter Athanas, Newport, VA (US);
John K. Bowen, Alexandria, VA (US);
Timothy G. Dunham, Roanoke, VA (US);
Justin D. Rice, Coral Springs, FL (US);
Matthew T. Shelburne, Christiansburg, VA (US);
Jorge A. Suris Pletri, Blacksburg, VA (US);
Jonathan Graf, Blacksburg, VA (US);
Virginia Tech Intellectual Properties, Inc., Blacksburg, VA (US);
Abstract
A method, and system, for reconfiguring an FPGA which has a static region and a dynamic region is provided. The method includes the steps of: (a) providing a dynamic module library having information of predetermined modules; (b) receiving a reconfiguration request external to the FPGA; (c) computing reconfiguration of the FPGA at a predetermined location using predetermined module information from the dynamic module library and the reconfiguration request, and generating reconfigurable partial bitstreams; and (d) sending partial bitstreams from the predetermined location to the FPGA to perform the reconfiguration.