Multi-clock system-on-chip with universal clock control modules for transition fault test at speed multi-core

Abstract

A multi-clock system-on-chip (D) comprises i) a core (CE) comprising asynchronous clock domains provided for exchanging test data therebetween, ii) a clock generator unit (CGU) arranged for delivering primary clock signals (clk-clko) for at least some of the clock domains, and iii) clock control modules (CCl-CCo), arranged respectively for defining the functional clock signals from the primary clock signals and from control signals (intended for setting the clock control modules (CCl) in a normal mode allowing test data transmission from the corresponding emitter clock domain to at least one receiver clock domain or a shift mode forbidding such a test data transmission). Each clock control module (CCl) is connected to a synchronization means (SM) arranged for switching it from the shift mode to the normal mode, and to a delay means (DM) arranged for putting back the emitter launch edge of a functional clock signal intended for the emitter clock domain when this clock control module (CCl) is set into the normal mode, in order this emitter launch edge be temporally located before each corresponding receiver capture edge of the clock signals intended for the receiver clock domains to which the emitter clock domain must transmit test data.